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ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
16 years 4 days ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
CORR
2011
Springer
188views Education» more  CORR 2011»
15 years 1 months ago
Planar Cycle Covering Graphs
We describe a new variational lower-bound on the minimum energy configuration of a planar binary Markov Random Field (MRF). Our method is based on adding auxiliary nodes to every...
Julian Yarkony, Alexander T. Ihler, Charless C. Fo...
ET
2002
90views more  ET 2002»
15 years 6 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ICIP
2000
IEEE
16 years 8 months ago
Optimal Design of Transform Coders and Quantizers for Image Classification
In a variety of applications (including automatic target recognition) image classification algorithms operate on compressed image data. This paper explores the design of optimal t...
Soumya Jana, Pierre Moulin
CEC
2009
IEEE
16 years 1 months ago
Evolutionary programming with ensemble of explicit memories for dynamic optimization
—This paper presents the evolutionary programming with an ensemble of memories to deal with optimization problems in dynamic environments. The proposed algorithm modifies a recen...
Ling Yu, Ponnuthurai N. Suganthan