431 search results - page 75 / 87 » Implementing the maximum of monotone algorithms |
166
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WOMPAT
2001
Springer
15 years 10 months ago
2001
Springer
In contrast to the common belief that OpenMP requires data-parallel extensions to scale well on architectures with non-uniform memory access latency, recent work has shown that it ...
144
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ASPDAC
2000
ACM
15 years 10 months ago
2000
ACM
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
186
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ISCAS
1994
IEEE
15 years 10 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
167
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ICDCS
2010
IEEE
15 years 9 months ago
2010
IEEE
: This paper presents a Least Popularly Used buffer cache algorithm to exploit both temporal locality and content locality of I/O requests. Popular data blocks are selected as refe...
153
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EMSOFT
2006
Springer
15 years 9 months ago
2006
Springer
Video kiosks increasingly contain powerful PC-like embedded processors, allowing them to display video at a high level of quality. Such video display, however, entails significant...