581 search results - page 7 / 117 » Implementing the Best Processor Cores |
154
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ISCA
2009
IEEE
16 years 16 days ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
143
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MICRO
1999
IEEE
15 years 10 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
135
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DDECS
2006
IEEE
15 years 9 months ago
2006
IEEE
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
150
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ICPP
2007
IEEE
16 years 6 days ago
2007
IEEE
In this paper, a novel packet classification scheme optimized for multi-core network processors is proposed. The algorithm, Explicit Cuttings (ExpCuts), adopts a hierarchical spac...
153
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NOCS
2007
IEEE
16 years 5 days ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...