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VEE
2005
ACM
119views Virtualization» more  VEE 2005»
16 years 12 days ago
A programmable microkernel for real-time systems
We present a new software system architecture for the implementation of hard real-time applications. The core of the system is a microkernel whose reactivity (interrupt handling a...
Christoph M. Kirsch, Marco A. A. Sanvido, Thomas A...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 11 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
SAGA
2009
Springer
16 years 1 months ago
Bounds for Multistage Stochastic Programs Using Supervised Learning Strategies
We propose a generic method for obtaining quickly good upper bounds on the minimal value of a multistage stochastic program. The method is based on the simulation of a feasible dec...
Boris Defourny, Damien Ernst, Louis Wehenkel
CGO
2008
IEEE
16 years 1 months ago
Modulo scheduling for highly customized datapaths to increase hardware reusability
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met ...
Kevin Fan, Hyunchul Park, Manjunath Kudlur, Scott ...
SIPS
2008
IEEE
16 years 1 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro