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FPT
2005
IEEE
198views Hardware» more  FPT 2005»
16 years 11 days ago
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
Wolfgang Klingauf, Robert Günzel
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
16 years 11 days ago
An 11M-triangles/sec 3D graphics clipping engine for triangle primitives
—This paper describes a clipping engine, which processes the view clipping, perspective division, and view-port mapping of 3D graphics. Complexity of polygon clipping algorithm c...
Jaewan Bae, Donghyun Kim, Lee-Sup Kim
170
Voted
CHES
2005
Springer
111views Cryptology» more  CHES 2005»
16 years 9 days ago
Hardware Acceleration of the Tate Pairing in Characteristic Three
Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core comp...
Philipp Grabher, Dan Page
EGH
2004
Springer
16 years 5 days ago
Squeeze: numerical-precision-optimized volume rendering
This paper discusses how to squeeze volume rendering into as few bits per operation as possible while still retaining excellent image quality. For each of the typical volume rende...
Ingmar Bitter, Neophytos Neophytou, Klaus Mueller,...
FPL
2004
Springer
95views Hardware» more  FPL 2004»
16 years 5 days ago
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platf...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...