5562 search results - page 741 / 1113 » Implementing Parallel Cell-DEVS |
175
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ICDCS
1999
IEEE
15 years 11 months ago
1999
IEEE
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
149
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ICPP
1999
IEEE
15 years 11 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
156
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ICPP
1999
IEEE
15 years 11 months ago
1999
IEEE
A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-...
285
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ARTS
1999
Springer
15 years 11 months ago
1999
Springer
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
184
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IEEEPACT
1999
IEEE
15 years 11 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...