5562 search results - page 736 / 1113 » Implementing Parallel Cell-DEVS |
159
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
167
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EUROPAR
2001
Springer
15 years 11 months ago
2001
Springer
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
192
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ICCS
2001
Springer
15 years 11 months ago
2001
Springer
Abstract. Parallel Computational Science and Engineering (CSE) applications often exhibit irregular structure and dynamic load patterns. Many such applications have been developed ...
152
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PACT
2001
Springer
15 years 11 months ago
2001
Springer
Abstract. This paper describes a mechanism for “fusing” concurrent invocations of exclusive methods. The target of our work is object-oriented languages with concurrent extensi...
164
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HPCA
2000
IEEE
15 years 11 months ago
2000
IEEE
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...