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IPPS
2005
IEEE
16 years 10 days ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
IPPS
2005
IEEE
16 years 10 days ago
Exploiting WSRF and WSRF.NET for Remote Job Execution in Grid Environments
The Web Service Resource Framework (WSRF) was announced in January 2004 as a new way for manipulating "stateful resources" to perform grid computing tasks using Web Serv...
Glenn S. Wasson, Marty Humphrey
IPPS
2005
IEEE
16 years 10 days ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
16 years 10 days ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ISPAN
2005
IEEE
16 years 10 days ago
P2P Architecture for Self-Atomic Memory
We propose an architecture for self-adjusting and self-healing atomic memory in highly dynamic systems exploiting peer-to-peer (p2p) techniques. Our approach, named SAM, brings to...
Emmanuelle Anceaume, Maria Gradinariu, Vincent Gra...