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ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
16 years 28 days ago
Matrix scheduler reloaded
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, ...
RTAS
2006
IEEE
16 years 20 days ago
An Interface Algebra for Real-Time Components
We present an assume-guarantee interface algebra for real-time components. In our formalism a component implements a set of task sequences that share a resource. A component inter...
Thomas A. Henzinger, Slobodan Matic
147
Voted
VTC
2006
IEEE
129views Communications» more  VTC 2006»
16 years 19 days ago
Practicable MIMO Capacity in Ideal Channels
— The impact of communications signal processing such as QAM modulations (instead of gaussian signals), finite block lengths (instead of infinitely long codes), and using simpl...
S. Amir Mirtaheri, Rodney G. Vaughan
INFOCOM
2005
IEEE
16 years 7 days ago
The impact of imperfect scheduling on cross-layer rate control in wireless networks
— In this paper, we study cross-layer design for rate control in multihop wireless networks. In our previous work, we have developed an optimal cross-layered rate control scheme ...
Xiaojun Lin, Ness B. Shroff
FPL
2005
Springer
111views Hardware» more  FPL 2005»
16 years 5 days ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....