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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 11 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
15 years 11 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
15 years 11 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
WISE
2002
Springer
15 years 11 months ago
An Update-Risk Based Approach to TTL Estimation in Web Caching
Web caching is an important technique for accelerating web applications and reducing the load on the web server and the network through local cache accesses. As in the traditional...
Jeong-Joon Lee, Kyu-Young Whang, Byung Suk Lee, Ji...
CODES
2009
IEEE
15 years 11 months ago
A tuneable software cache coherence protocol for heterogeneous MPSoCs
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
Frank E. B. Ophelders, Marco Bekooij, Henk Corpora...
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