72 search results - page 5 / 15 » Impact of memory hierarchy on program partitioning and sched... |
165
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OOPSLA
2005
Springer
15 years 11 months ago
2005
Springer
It is now well established that the device scaling predicted by Moore’s Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the...
147
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HPDC
2007
IEEE
16 years 8 days ago
2007
IEEE
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
156
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ASPLOS
2010
ACM
16 years 24 days ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
165
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ICPADS
2006
IEEE
15 years 12 months ago
2006
IEEE
In this paper, we utilize a bandwidth-centric job communication model that captures the interaction and impact of simultaneously co-allocating jobs across multiple clusters. We ma...
153
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DATE
2009
IEEE
16 years 21 days ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...