1595 search results - page 158 / 319 » Illustrative Parallel Coordinates |
154
click to vote
EUROPAR
2009
Springer
16 years 1 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
169
click to vote
IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
193
click to vote
IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
148
click to vote
ICS
1999
Tsinghua U.
15 years 11 months ago
1999
Tsinghua U.
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
207
click to vote
CPE
1998
Springer
15 years 10 months ago
1998
Springer
This paper describes a modular and scalable simulation environment, called GloMoSim, to evaluate end-to-end performance of integrated wired and wireless networks. GloMoSim has been...