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FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
14 years 10 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
JMLR
2012
13 years 9 months ago
Message-Passing Algorithms for MAP Estimation Using DC Programming
We address the problem of finding the most likely assignment or MAP estimation in a Markov random field. We analyze the linear programming formulation of MAP through the lens of...
Akshat Kumar, Shlomo Zilberstein, Marc Toussaint
HPDC
2012
IEEE
13 years 9 months ago
Exploring the performance and mapping of HPC applications to platforms in the cloud
This paper presents a scheme to optimize the mapping of HPC applications to a set of hybrid dedicated and cloud resources. First, we characterize application performance on dedica...
Abhishek Gupta, Laxmikant V. Kalé, Dejan S....
TREC
2007
15 years 7 months ago
Exegy at TREC 2007 Million Query Track
Exegy’s submission for the TREC 2007 million query track consisted of results obtained by running the queries against the raw data, i.e., the data was not indexed. The hardwarea...
Naveen Singla, Ronald S. Indeck
DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
15 years 10 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka