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ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
15 years 11 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 11 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
145
Voted
CLADE
2004
IEEE
15 years 10 months ago
Grid Service for Visualization and Analysis of Remote Fusion Data
Simulations and experiments in the fusion and plasma physics community generate large datasets at remote sites. Visualization and analysis of these datasets are difficult because ...
Svetlana G. Shasharina, Nanbor Wang, John R. Cary
CONCUR
2006
Springer
15 years 10 months ago
On Interleaving in Timed Automata
We propose a remedy to that part of the state-explosion problem for timed automata which is due to interleaving of actions. We prove the following quite surprising result: the unio...
Ramzi Ben Salah, Marius Bozga, Oded Maler