3161 search results - page 154 / 633 » Hybrid results merging |
166
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
153
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
154
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INFOVIS
2002
IEEE
15 years 11 months ago
2002
IEEE
Many clustering and layout techniques have been used for structuring and visualising complex data. This paper is inspired by a number of such contemporary techniques and presents ...
150
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ISQED
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
185
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. We investigate the performance of two approaches for matrix inversion based on Gaussian (LU factorization) and Gauss-Jordan eliminations. The target architecture is a cur...