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DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 12 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
SIGSOFT
2000
ACM
15 years 11 months ago
Compiler and tool support for debugging object protocols
We describe an extension to the Java programming language that supports static conformance checking and dynamic debugging of object "protocols," i.e., sequencing constra...
Sergey Butkevich, Marco Renedo, Gerald Baumgartner...
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 11 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
CPAIOR
2006
Springer
15 years 10 months ago
Online Stochastic Reservation Systems
This paper considers online stochastic reservation problems, where requests come online and must be dynamically allocated to limited resources in order to maximize profit. Multi-k...
Pascal Van Hentenryck, Russell Bent, Yannis Vergad...
DAC
2005
ACM
15 years 8 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson