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ASPLOS
2010
ACM
16 years 1 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
SERA
2009
Springer
16 years 1 months ago
Syntactic and Semantic Prediction in Dynamic Languages
In the context of computer programming, the importance of computer assistance is being understood by many developer communities. Developers are e.g. using the same well known expre...
Jakub Mísek, Filip Zavoral
IEEEPACT
2007
IEEE
16 years 1 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
JAVA
2001
Springer
15 years 11 months ago
Supporting dynamic parallel object arrays
We present efficient support for generalized arrays of parallel data driven objects. Array elements are regular C++ objects, and are scattered across the parallel machine. An indi...
Orion Sky Lawlor, Laxmikant V. Kalé
ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
15 years 11 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...