Existing clock synchronization algorithms assume a bounded clock reading error. This, in turn, results in an inflexible design that typically requires node crashes whenever the g...
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
Hypertext is being used more and more for on-line course texts. But the navigational freedom offered by a rich link structure is a burdon for students who need guidance throughout...
Building the hardware for a high-performance distributed computer system is a lot easier than building its software. In this paper we describe a model for programtributed systems ...
Andrew S. Tanenbaum, Henri E. Bal, M. Frans Kaasho...
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...