—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
A novel approach for similarity search on the protein structure databases is proposed. PADS (Protein Alignment by Directional shape Signatures) incorporates the three dimensional ...
S. Alireza Aghili, Divyakant Agrawal, Amr El Abbad...
We describe race-free properties of a hardware description language called GEZEL. The language describes networks of cycle-true finite-state-machines with datapaths (FSMDs). We de...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...