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HIPEAC
2010
Springer
16 years 3 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar
ALT
2004
Springer
16 years 3 months ago
Relative Loss Bounds and Polynomial-Time Predictions for the k-lms-net Algorithm
We consider a two-layer network algorithm. The first layer consists of an uncountable number of linear units. Each linear unit is an LMS algorithm whose inputs are first “kerne...
Mark Herbster
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
16 years 3 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
16 years 3 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
154
Voted
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 3 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata