38 search results - page 1 / 8 » High-level test synthesis for delay fault testability |
179
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EVOW
2001
Springer
15 years 10 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
137
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VTS
1999
IEEE
15 years 10 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
131
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
146
Voted
DATE
2007
IEEE
16 years 3 days ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
159
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...