64 search results - page 2 / 13 » High-Performance Extendable Instruction Set Computing |
183
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APCSAC
2006
IEEE
16 years 1 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
206
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SC
1992
ACM
15 years 11 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
237
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IPPS
2010
IEEE
15 years 5 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
199
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ARC
2006
Springer
15 years 11 months ago
2006
Springer
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
194
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IPPS
2000
IEEE
15 years 11 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...