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» High-Level Power Modeling, Estimation, and Optimization
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ICC
2008
IEEE
115views Communications» more  ICC 2008»
16 years 9 days ago
Joint Power Scheduling and Estimator Design for Sensor Networks Across Parallel Channels
—This paper addresses the joint estimator and power optimization problem for a sensor network whose mission is to estimate an unknown parameter. We assume a two-hop network where...
Lauren M. Huie, Xiang He, Aylin Yener
DAC
2003
ACM
16 years 6 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
SAC
2005
ACM
15 years 11 months ago
Efficient placement and routing in grid-based networks
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...
Roozbeh Jafari, Foad Dabiri, Bo-Kyung Choi, Majid ...
ISLPED
1996
ACM
102views Hardware» more  ISLPED 1996»
15 years 10 months ago
High-level power estimation and the area complexity of Boolean functions
Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (...
Mahadevamurty Nemani, Farid N. Najm
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
16 years 2 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He