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ICDCS
2009
IEEE
15 years 4 months ago
Selective Protection: A Cost-Efficient Backup Scheme for Link State Routing
In recent years, there are substantial demands to reduce packet loss in the Internet. Among the schemes proposed, finding backup paths in advance is considered to be an effective ...
Meijia Hou, Dan Wang, Mingwei Xu, Jiahai Yang
CF
2010
ACM
15 years 12 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
ICDCS
2011
IEEE
14 years 6 months ago
Economical and Robust Provisioning of N-Tier Cloud Workloads: A Multi-level Control Approach
—Resource provisioning for N-tier web applications in Clouds is non-trivial due to at least two reasons. First, there is an inherent optimization conflict between cost of resour...
PengCheng Xiong, Zhikui Wang, Simon Malkowski, Qin...
EUROSYS
2010
ACM
16 years 3 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li