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» High performance computing through parallel processing
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ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
HPCA
2006
IEEE
16 years 7 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
ICDCS
2009
IEEE
16 years 4 months ago
The Taming of the Shrew: Mitigating Low-Rate TCP-Targeted Attack
A Shrew attack, which uses a low-rate burst carefully designed to exploit TCP’s retransmission timeout mechanism, can throttle the bandwidth of a TCP flow in a stealthy manner....
Chia-Wei Chang, Seungjoon Lee, B. Lin, Jia Wang
HPCA
2007
IEEE
16 years 1 months ago
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Albert Meixner, Daniel J. Sorin
ICN
2005
Springer
16 years 11 days ago
Fault Free Shortest Path Routing on the de Bruijn Networks
It is shown that the de Bruijn graph (dBG) can be used as an architecture for interconnection networks and a suitable structure for parallel computation. Recent works have classiï¬...
Ngoc Chi Nguyen, Vo Dinh Minh Nhat, Sungyoung Lee