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IAJIT
2010
107views more  IAJIT 2010»
15 years 5 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
15 years 11 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou
NIPS
2001
15 years 8 months ago
Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines
A mixed-signal paradigm is presented for high-resolution parallel innerproduct computation in very high dimensions, suitable for efficient implementation of kernels in image proce...
Roman Genov, Gert Cauwenberghs
165
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ANCS
2008
ACM
15 years 8 months ago
Performing time-sensitive network experiments
Time-sensitive network experiments are difficult. There are major challenges involved in generating high volumes of sufficiently realistic traffic. Additionally, accurately measur...
Neda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick...
MSWIM
2006
ACM
16 years 24 days ago
Estimation of perceived quality of service for applications on IPv6 networks
To provide high quality service to future Internet applications, IPv6 performance measurements are needed. However, to the best of our knowledge, IPv6 delay and loss performance e...
Xiaoming Zhou, Henk Uijterwaal, Robert E. Kooij, P...