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HPCA
2009
IEEE
16 years 7 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
ASPLOS
1998
ACM
15 years 11 months ago
A Cost-Effective, High-Bandwidth Storage Architecture
This paper describes the Network-Attached Secure Disk (NASD) storage architecture, prototype implementations of NASD drives, array management for our architecture, and three files...
Garth A. Gibson, David Nagle, Khalil Amiri, Jeff B...
CBMS
2006
IEEE
16 years 26 days ago
A Framework for Web-Based Interactive Applications of High-Resolution 3D Medical Image Data
With the advances in medical imaging devices, large volumes of high-resolution 3D medical image data have been produced. These high-resolution 3D data are very large in size, and ...
Danzhou Liu, Kien A. Hua, Kiminobu Sugaya
GRAPHITE
2007
ACM
15 years 8 months ago
Mode-splitting for highly detailed, interactive liquid simulation
This work introduces a new technique for highly detailed, interactive liquid simulations. Similar to the mode-splitting method (used e.g. in oceanography), we separate the simulat...
H. Cords
FPL
2006
Springer
127views Hardware» more  FPL 2006»
15 years 10 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...