An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IB...
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, Wi...
This paper explores the model of providing a common overlay structure management layer to assist the construction of large-scale wide-area Internet services. To this end, we propo...
Parallel tools rely on graphical techniques to improve the quality of user interaction. In this paper, we explore how visualization and direct manipulation can be exploited in para...
The paper presents a fail-safe mobility management and a collision prevention platform for a group of asynchronous cooperative mobile robots. The fail-safe platform consists of a ...