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2000
Tsinghua U.
15 years 11 months ago
Improving parallel system performance by changing the arrangement of the network links
The Midimew network is an excellent contender for implementing the communication subsystem of a high performance computer. This network is an optimal 2D topology in the sense ther...
Valentin Puente, Cruz Izu, José A. Gregorio...
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 10 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
15 years 10 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
CORR
2010
Springer
83views Education» more  CORR 2010»
15 years 7 months ago
Investigating the Performance of an Adiabatic Quantum Optimization Processor
We calculate median adiabatic times (in seconds) of a specific superconducting adiabatic quantum processor for an NP-hard Ising spin glass instance class with up to N = 128 binary ...
Geordie Rose, Kamran Karimi, Neil G. Dickson, Fira...
CAL
2006
15 years 7 months ago
A case for fault tolerance and performance enhancement using chip multi-processors
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
Huiyang Zhou