Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
In this paper, we model Probabilistic Packet Marking (PPM) schemes for IP traceback as an identification problem of a large number of markers. Each potential marker is associated ...
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
This paper presents results from the first double-directional measurements of the Multiple-Input Multiple-Output (MIMO) peer-to-peer radio channel in the 300 MHz frequency range....
Gunnar Eriksson, Fredrik Tufvesson, Andreas F. Mol...