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HPDC
1997
IEEE
15 years 11 months ago
Packing Messages as a Tool for Boosting the Performance of Total Ordering Protocols
This paper compares the throughput and latency of four protocols that provide total ordering. Two of these protocols are measured with and without message packing. We used a techn...
Roy Friedman, Robbert van Renesse
IPPS
1997
IEEE
15 years 11 months ago
An Accurate Model for the Performance Analysis of Deterministic Wormhole Routing
We present a new analytical approach for the performance evaluation of asynchronous wormhole routing in k-ary n-cubes. Through the analysis of network flows, our methodology furni...
Bruno Ciciani, Claudio Paolucci, Michele Colajanni
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
15 years 11 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
CONPAR
1994
15 years 11 months ago
The Rewrite Rule Machine Node Architecture and Its Performance
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
Patrick Lincoln, José Meseguer, Livio Ricci...
MICRO
1992
IEEE
99views Hardware» more  MICRO 1992»
15 years 11 months ago
An investigation of the performance of various dynamic scheduling techniques
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
Michael Butler, Yale N. Patt