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JPDC
2006
141views more  JPDC 2006»
15 years 6 months ago
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
Secure processor architectures enable new sets of applications such as commercial grid computing, software copy protection and secure mobile agents by providing secure computing e...
Chenghuai Lu, Tao Zhang, Weidong Shi, Hsien-Hsin S...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
16 years 1 months ago
A new hybrid solution to boost SAT solver performance
Due to the widespread demands for efficient SAT solvers in Electronic Design Automation applications, methods to boost the performance of the SAT solver are highly desired. We pr...
Lei Fang, Michael S. Hsiao
MICRO
1997
IEEE
110views Hardware» more  MICRO 1997»
15 years 11 months ago
The Design and Performance of a Conflict-Avoiding Cache
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
Nigel P. Topham, Antonio González, Jos&eacu...
ICIP
2000
IEEE
16 years 8 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...
GLOBECOM
2008
IEEE
16 years 1 months ago
Performance Comparison between NEMO BSP and SINEMO
Abstract—IETF has proposed Mobile IPv6-based Network Mobility (NEMO) basic support protocol (BSP) to support network mobility. NEMO BSP inherits all the drawbacks of Mobile IPv6,...
Md. Sazzadur Rahman, Outman Bouidel, Mohammed Atiq...