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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 10 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
TPDS
2008
113views more  TPDS 2008»
15 years 6 months ago
Evaluating a High-Level Parallel Language (GpH) for Computational GRIDs
Computational Grids potentially offer low cost, readily available, and large-scale high-performance platforms. For the parallel execution of programs, however, computational GRIDs ...
Abdallah Al Zain, Philip W. Trinder, Greg Michaels...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
TASLP
2008
176views more  TASLP 2008»
15 years 6 months ago
Analysis of Minimum Distances in High-Dimensional Musical Spaces
Abstract--We propose an automatic method for measuring content-based music similarity, enhancing the current generation of music search engines and recommender systems. Many previo...
Michael Casey, Christophe Rhodes, Malcolm Slaney
ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung