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CLEIEJ
2010
15 years 4 months ago
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard
This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this...
Felipe Sampaio, Daniel Palomino, Robson Dornelles,...
CEC
2008
IEEE
16 years 1 months ago
A fast high quality pseudo random number generator for graphics processing units
—Limited numerical precision of nVidia GeForce 8800 GTX and other GPUs requires careful implementation of PRNGs. The Park-Miller PRNG is programmed using G80’s native Value4f ï...
William B. Langdon
105
Voted
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
15 years 12 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
DAC
2004
ACM
16 years 7 months ago
An integrated hardware/software approach for run-time scratchpad management
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...
Francesco Poletti, Paul Marchal, David Atienza, Lu...
IPPS
2006
IEEE
16 years 20 days ago
Parallel ICA methods for EEG neuroimaging
HiPerSAT, a C++ library and tools, processes EEG data sets with ICA (Independent Component Analysis) methods. HiPerSAT uses BLAS, LAPACK, MPI and OpenMP to achieve a high performa...
D. B. Keith, C. C. Hoge, Robert M. Frank, Allen D....