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ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
16 years 4 days ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
15 years 11 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
SAC
2008
ACM
15 years 6 months ago
Runtime concepts for the C++ standard template library
A key benefit of generic programming is its support for producing modules with clean separation. In particular, generic algorithms are written to work with a wide variety of unmod...
Peter Pirkelbauer, Sean Parent, Mat Marcus, Bjarne...
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
14 years 6 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
CASES
2006
ACM
16 years 16 days ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...