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EUROPAR
2010
Springer
15 years 6 months ago
Source-to-Source Optimization of CUDA C for GPU Accelerated Cardiac Cell Modeling
Large and complex systems of ordinary differential equations (ODEs) arise in diverse areas of science and engineering, and pose special challenges on a streaming processor owing to...
Fred V. Lionetti, Andrew D. McCulloch, Scott B. Ba...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 29 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
DAC
2002
ACM
16 years 7 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...
PLDI
2006
ACM
16 years 15 days ago
Practical dynamic software updating for C
Software updates typically require stopping and restarting an application, but many systems cannot afford to halt service, or would prefer not to. Dynamic software updating (DSU) ...
Iulian Neamtiu, Michael W. Hicks, Gareth Stoyle, M...
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
16 years 3 days ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...