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SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
16 years 14 days ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
16 years 17 days ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
IPPS
2009
IEEE
16 years 1 months ago
Parallel short sequence mapping for high throughput genome sequencing
Doruk Bozdag, Catalin C. Barbacioru, Ümit V. ...