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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 10 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
IPPS
2006
IEEE
16 years 10 days ago
Towards building a highly-available cluster based model for high performance computing
In recent years, we have witnessed a growing interest in high performance computing (HPC) using a cluster of workstations. However, many challenges remain to be resolved before th...
Azzedine Boukerche, Raed Al-Shaikh, Mirela Sechi M...
CATA
2003
15 years 7 months ago
A Task Migration Scheme for High Performance Real-Time Cluster System
In a real-time system, it is attractive to use cluster computing system for realizing high performance and high availability. The objectives of the real-time clusters are maximize...
Makoto Suzuki, Hidenori Kobayashi, Nobuyuki Yamasa...
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
16 years 1 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...
ICCS
2005
Springer
15 years 11 months ago
Introducing Design Patterns, Graphical User Interfaces and Threads Within the Context of a High Performance Computing Applicatio
The cross fertilization of methods and techniques between different subject areas in the undergraduate curriculum is a challenge, especially at the more advanced levels. This paper...
James Roper, Alistair P. Rendell