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IPPS
2006
IEEE
16 years 23 days ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...
156
Voted
ISCAS
2006
IEEE
146views Hardware» more  ISCAS 2006»
16 years 23 days ago
CMOS image sensor with analog gamma correction using nonlinear single-slope ADC
A human eye has the logarithmic response over wide range of light intensity. Although the gain can be set high to Dout identify details in darker area on the image, this results in...
Seogheon Ham, Yonghee Lee, Wunki Jung, Seunghyun L...
MICRO
2006
IEEE
79views Hardware» more  MICRO 2006»
16 years 23 days ago
Fair Queuing Memory Systems
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
VTC
2006
IEEE
206views Communications» more  VTC 2006»
16 years 23 days ago
BER Performance Improvement with Joint Angle-Delay-Polarization Estimation of Multipath Channel Parameters
Abstract— In mobile telecommunications, the quality of demodulation is strongly impacted by channel estimation. The Joint Angle, Delay and Polarization Estimation (JADPE) problem...
Cristian Tohanean, José Picheral
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
16 years 22 days ago
DraXRouter: global routing in X-Architecture with dynamic resource assignment
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hon...