619 search results - page 67 / 124 » High Performance Integrated Network Communications Architect... |
149
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
159
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HPCA
2001
IEEE
16 years 6 months ago
2001
IEEE
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
164
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ASPDAC
2012
ACM
14 years 1 months ago
2012
ACM
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
153
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MOBIHOC
2009
ACM
16 years 6 months ago
2009
ACM
Most future large-scale sensor networks are expected to follow a two-tier architecture which consists of resource-rich master nodes at the upper tier and resource-poor sensor node...
164
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DFT
2008
IEEE
16 years 18 days ago
2008
IEEE
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...