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IPPS
2007
IEEE
16 years 9 days ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
JSA
2010
158views more  JSA 2010»
15 years 24 days ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
IPPS
2007
IEEE
16 years 9 days ago
A Cost-Effective, High Bandwidth Server I/O network Architecture for Cluster Systems
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
Hsing-bung Chen, Gary Grider, Parks Fields
SAINT
2005
IEEE
15 years 11 months ago
Channel-Based Connectivity Management Middleware for Seamless Integration of Heterogeneous Wireless Networks
This paper presents a middleware architecture for the adaptable management of heterogeneous wireless resources. The main application of the proposed architecture is the optimal ut...
Jun-Zhao Sun, Jukka Riekki, Marko Jurmu, Jaakko J....
INFOCOM
1999
IEEE
15 years 10 months ago
High Performance IP Routing Table Lookup using CPU Caching
Wire-speed IP (Internet Protocol) routers require very fast routing table lookup for incoming IP packets. The routing table lookup operation is time consuming because the part of ...
Tzi-cker Chiueh, Prashant Pradhan