Sciweavers

174 search results - page 16 / 35
» High Performance FPGA Implementation of the Mersenne Twister
Sort
View
JVCIR
2008
92views more  JVCIR 2008»
15 years 6 months ago
Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The soft...
Dionisis Chaikalis, Nikos Sgouros, Dimitris Maroul...
CISS
2008
IEEE
16 years 16 days ago
Accelerated costas array enumeration using FPGAs
Abstract— Costas array enumeration is an NP-complete problem with a highly parallelize-able solution. This paper examines the implementation of a solution to this problem on an F...
Jim Devlin, Scott Rickard
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 10 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
15 years 9 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
IPPS
2006
IEEE
16 years 2 days ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...