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HPCC
2009
Springer
15 years 11 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
HPDC
2010
IEEE
15 years 7 months ago
Detouring and replication for fast and reliable internet-scale stream processing
iFlow is a replication-based system that can achieve both fast and reliable processing of high volume data streams on the Internet scale. iFlow uses a low degree of replication in...
Christopher McConnell, Fan Ping, Jeong-Hyon Hwang
ICCV
2011
IEEE
14 years 6 months ago
From Learning Models of Natural Image Patches to Whole Image Restoration
Learning good image priors is of utmost importance for the study of vision, computer vision and image processing applications. Learning priors and optimizing over whole images can...
Daniel Zoran, Yair Weiss

Publication
200views
17 years 5 months ago
Dynamic Queue Control Functions for ATM ABR Switch Schemes: Design and Analysis
The main goals of a switch scheme are high utilization, low queuing delay and fairness. To achieve high utilization the switch scheme can maintain non-zero (small) queues in steady...
Bobby Vandalore, Raj Jain, Rohit Goyal, Sonia Fahm...
ICPR
2004
IEEE
16 years 7 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker