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HIPEAC
2011
Springer
14 years 6 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
TIT
2002
70views more  TIT 2002»
15 years 6 months ago
High-rate codes that are linear in space and time
Multiple-antenna systems that operate at high rates require simple yet effective space-time transmission schemes to handle the large traffic volume in real time. At rates of tens ...
Babak Hassibi, Bertrand M. Hochwald
VALUETOOLS
2006
ACM
164views Hardware» more  VALUETOOLS 2006»
16 years 22 days ago
Analysis of Markov reward models using zero-suppressed multi-terminal BDDs
High-level stochastic description methods such as stochastic Petri nets, stochastic UML statecharts etc., together with specifications of performance variables (PVs), enable a co...
Kai Lampka, Markus Siegle
WADS
1989
Springer
84views Algorithms» more  WADS 1989»
15 years 10 months ago
Skip Lists: A Probabilistic Alternative to Balanced Trees
rees can be used for representing abstract data types such as dictionaries and ordered lists. They work well when the elements are inserted in a random order. Some sequences of ope...
William Pugh
IJVR
2008
106views more  IJVR 2008»
15 years 6 months ago
Improved View Frustum Culling Technique for Real-Time Virtual Heritage Application
Real-time virtual heritage application is normally executed with a high performance computer system. This is due to the complexity and highly computational cost which makes such sy...
Mohd Shahrizal Sunar, Abdullah Mohd Zin, Tengku M....