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ICS
2009
Tsinghua U.
15 years 11 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
CONEXT
2008
ACM
15 years 8 months ago
Troubleshooting chronic conditions in large IP networks
Chronic network conditions are caused by performance impairing events that occur intermittently over an extended period of time. Such conditions can cause repeated performance deg...
Ajay Mahimkar, Jennifer Yates, Yin Zhang, Aman Sha...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
16 years 1 days ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ORGSCI
2010
92views more  ORGSCI 2010»
15 years 4 months ago
Are Technology-Intensive Industries More Dynamically Competitive? No and Yes
A growing body of research in management and related public policy fields concludes that the 1980s and 1990s saw greater dynamic competition throughout technology−intensive (“...
Paul M. Vaaler, Gerry McNamara
HPCA
2009
IEEE
16 years 7 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
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