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HPCA
2002
IEEE
15 years 11 months ago
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
CVPR
2004
IEEE
16 years 8 months ago
Thermal Face Recognition in an Operational Scenario
We present results on the latest advances in thermal infrared face recognition, and its use in combination with visible imagery. Previous research has shown high performance under...
Diego A. Socolinsky, Andrea Selinger
ISPA
2007
Springer
16 years 1 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ICPP
2007
IEEE
16 years 1 months ago
Energy-Efficient Scheduling for Parallel Applications Running on Heterogeneous Clusters
High performance clusters have been widely used to provide amazing computing capability for both commercial and scientific applications. However, huge power consumption has preven...
Ziliang Zong, Xiao Qin, Xiaojun Ruan, Kiranmai Bel...
IPPS
2006
IEEE
16 years 26 days ago
An experimental study of optimizing bioinformatics applications
As bioinformatics is an emerging application of high performance computing, this paper first evaluates the memory performance of several representative bioinformatics application...
Guangming Tan, Lin Xu, Shengzhong Feng, Ninghui Su...