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VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
16 years 7 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
ICPP
2008
IEEE
16 years 1 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
DSN
2007
IEEE
16 years 1 months ago
Web Services Wind Tunnel: On Performance Testing Large-Scale Stateful Web Services
New versions of existing large-scale web services such as Passport.com© have to go through rigorous performance evaluations in order to ensure a high degree of availability. Perf...
Marcelo De Barros, Jing Shiau, Chen Shang, Kenton ...
IPPS
2006
IEEE
16 years 20 days ago
Dynamic performance prediction of an adaptive mesh application
While it is possible to accurately predict the execution time of a given iteration of an adaptive application, it is not generally possible to predict the data-dependent adaptive ...
Mark M. Mathis, Darren J. Kerbyson
HIPEAC
2009
Springer
15 years 11 months ago
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
Abstract. In transactional memory, aborted transactions reduce performance, and waste computing resources. Ideally, concurrent execution of transactions should be optimally ordered...
Mohammad Ansari, Mikel Luján, Christos Kots...