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» High Performance Architectures and Compilers
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CASES
2003
ACM
15 years 11 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
16 years 9 days ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
CLUSTER
2002
IEEE
15 years 11 months ago
Scalable Resource Management in High Performance Computers
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
Eitan Frachtenberg, Fabrizio Petrini, Juan Fern&aa...
SPAA
1996
ACM
15 years 10 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
CASCON
2008
164views Education» more  CASCON 2008»
15 years 7 months ago
High performance XML parsing using parallel bit stream technology
Parabix (parallel bit streams for XML) is an open-source XML parser that employs the SIMD (single-instruction multiple-data) capabilities of modern-day commodity processors to del...
Robert D. Cameron, Kenneth S. Herdy, Dan Lin