2852 search results - page 463 / 571 » High Performance Architectures and Compilers |
169
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ISPASS
2007
IEEE
16 years 17 days ago
2007
IEEE
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
167
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GLOBECOM
2006
IEEE
16 years 10 days ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
169
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ICPPW
2006
IEEE
16 years 10 days ago
2006
IEEE
Abstract— Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on s...
180
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INFOCOM
2006
IEEE
16 years 9 days ago
2006
IEEE
— The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high line speeds. A central problem in designing an input-queued swit...
159
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CASES
2006
ACM
16 years 8 days ago
2006
ACM
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...