Sciweavers

2852 search results - page 228 / 571
» High Performance Architectures and Compilers
Sort
View
GLVLSI
2010
IEEE
220views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Thermal-aware voltage droop compensation for multi-core architectures
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
Jia Zhao, Basab Datta, Wayne P. Burleson, Russell ...
PPOPP
1993
ACM
15 years 10 months ago
Integrating Message-Passing and Shared-Memory: Early Experience
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
David A. Kranz, Kirk L. Johnson, Anant Agarwal, Jo...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 10 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
15 years 10 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
CCGRID
2001
IEEE
15 years 10 months ago
Parallel I/O Support for HPF on Clusters
Clusters of workstations are a popular alternative to integrated parallel systems designed and built by a vendor. Besides their huge cumulative processing power, they also provide...
Peter Brezany, Viera Sipková